Looking for the best equivalents of prefetch instructions for ia32, ia64, amd64, and powerpc

Question

I'm looking at some slightly confused code that's attempted a platform abstraction of prefetch instructions, using various compiler builtins. It appears to be based on powerpc semantics initially, with Read and Write prefetch variations using dcbt and dcbtst respectively (both of these passing TH=0 in the new optional stream opcode).

On ia64 platforms we've got for read:

__lfetch(__lfhint_nt1, pTouch)

wherease for write:

__lfetch_excl(__lfhint_nt1, pTouch)

This (read vs. write prefetching) appears to match the powerpc semantics fairly well (with the exception that ia64 allows for a temporal hint).

Somewhat curiously the ia32/amd64 code in question is using

prefetchnta

Not

prefetchnt1

as it would if that code were to be consistent with the ia64 implementations (#ifdef variations of that in our code for our (still live) hpipf port and our now dead windows and linux ia64 ports).

Since we are building with the intel compiler I should be able to many of our ia32/amd64 platforms consistent by switching to the xmmintrin.h builtins:

_mm_prefetch( (char *)pTouch, _MM_HINT_NTA )
_mm_prefetch( (char *)pTouch, _MM_HINT_T1 )

... provided I can figure out what temporal hint should be used.

Questions:

• Are there read vs. write ia32/amd64 prefetch instructions? I don't see any in the instruction set reference.

• Would one of the nt1, nt2, nta temporal variations be preferred for read vs. write prefetching?

• Any idea if there would have been a good reason to use the NTA temporal hint on ia32/amd64, yet T1 on ia64?

Answer 1

• Are there read vs. write ia32/amd64 prefetch instructions? I don't see any in the instruction set reference.

Some systems support the prefetchw instructions for writes

• Would one of the nt1, nt2, nta temporal variations be preferred for read vs. write prefetching?

If the line is exclusively used by the calling thread, it shouldn't matter how you bring the line, both reads and writes would be able to use it. The benefit for prefetchw mentioned above is that it will bring the line and give you ownership on it, which may take a while if the line was also used by another core. The hint level on the other hand is orthogonal with the MESI states, and only affects how long would the prefetched line survive. This matters if you prefetch long ahead of the actual access and don't want to prefetch to get lost in that duration, or alternatively - prefetch right before the access, and don't want the prefetches to thrash your cache too much.

• Any idea if there would have been a good reason to use the NTA temporal hint on ia32/amd64, yet T1 on ia64?

Just speculating - perhaps the larger caches and aggressive memory BW are more vulnerable to bad prefetching and you'd want to reduce the impact through the non-temporal hint. Consider that your prefetcher is suddenly set loose to fetch anything it can, you'd end up swamped in junk prefetches that would through away lots of useful cachelines. The NTA hint makes them overrun each other, leaving the rest undamaged.

Of course this may also be just a bug, I can't tell for sure, only whoever developed the compiler, but it might make sense for the reason above.