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From a previous question on this forum, I learned that in most of the memory systems, L1 cache is a subset of the L2 cache means any entry removed from L2 is also removed from L1.
So now my question is how do I determine a corresponding entry in L1 cache for an entry in the L2 cache. The only information stored in the L2 entry is the tag information. Based on this tag information, if I re-create the addr it may span multiple lines in the L1 cache if the line-sizes of L1 and L2 cache are not same.
Does the architecture really bother about flushing both the lines or it just maintains L1 and L2 cache with the same line-size.
I understand that this is a policy decision but I want to know the commonly used technique.
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The cache line is generally fixed in size, typically ranging from 16 to 256 bytes. The effectiveness of the line size depends on the application, and cache circuits may be configurable to a different line size by the system designer.
There are 4 cores reported, then the total size of L1 cache = 4 X 64 KB = 256 KB.
Intel uses an L1 cache with a latency of 3 cycles. The L2 cache is shared between one or more L1 caches and is often much, much larger.
The L2 cache is 16-way set-associative of configurable size. The cache is physically-addressed. The cache sizes are configurable with sizes of 512KB, 1MB, 2MB, and 4MB.
Cache-Lines size is (typically) 64 bytes.
Moreover, take a look at this very interesting article about processors caches: Gallery of Processor Cache Effects
You will find the following chapters:
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