Is `timescale a preprocessor instruction?

Question

All Verilog lines of code that start with the character ` seem to be preprocessor instructions. However `timescale seems to be an odd one out, maybe.

Is `timescale a preprocessor instruction? If it is, what is it replaced by?

Answer 1

In Verilog, the backtick denotes a compiler directive. These are evaluated when the Verilog source code is compiled. `timescale sets the time unit and time precision for the modules which follow it in the source code.

`timescale does not do text macro substitution, as `define does.

Refer to the IEEE Standard (1800-2009, for example) for further details.