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Eg: a common device module's Makefile
obj-m:=jc.o default: $(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules clean: $(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules clean I consider if I can set CFLAGS to the file. When I change default section to
$(MAKE) -O2 -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules But it didn't work.
Any help? Thanks a lot.
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The top Makefile is responsible for building two major products: vmlinux (the resident kernel image) and modules (any module files). It builds these goals by recursively descending into the subdirectories of the kernel source tree. The list of subdirectories which are visited depends upon the kernel configuration.
$(obj-m) specifies object files which are built as loadable kernel modules. A module may be built from one source file or several source files. In the case of one source file, the kbuild makefile simply adds the file to $(obj-m).
obj-y += something/ This means that kbuild should go into the directory "something". Once it moves to this directory, it looks at the Makefile in "something" to decide what objects should be built. It is analogous to saying- go to the directory "something" and execute "make"
-O2 would be an option to make (or $(MAKE), as you're using it) in what you tried. Obviously, the compiler (probably gcc) needs this flag, not make.
Kbuild understands a make variable named CFLAGS_modulename.o to add specific C flags when compiling this unit. In your case, your module object will be jc.o, so you can specify:
CFLAGS_jc.o := -O2 and it should work. Add V=1 to your $(MAKE) lines to get a verbose output and you should see -O2 when jc.c is being compiled.
You can find more about compiling modules in the official documentation.
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You can also use
ccflags-y := -O2 This will be applied to all of the source files compiled for your module with the Makefile. This is indirectly documented in the link provided by eepp in Section 4.2
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