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Is it possible to define more than one conditional in one {$IFDEF} directive ?
I would like to have syntax like this:
{$IFDEF Condition1 OR Condition2} DoSomething; {$ENDIF} {$IFDEF Condition1 AND Condition2} DoSomethingElse; {$ENDIF} Thanks
886
Syntax. Conditional compilation can be achieved with Verilog `ifdef and `ifndef keywords. These keywords can appear anywhere in the design and can be nested one inside the other.
The meaning of #ifdef is that the code inside the block will be included in the compilation only if the mentioned preprocessor macro is defined. Similarily #if means that the block will be included only if the expression evaluates to true (when replacing undefined macros that appears in the expression with 0).
#if checks for the value of the symbol, while #ifdef checks the existence of the symbol (regardless of its value).
Use the #ifdef statement when you want to compile a section only if a specified expression has been defined with #define. Use #ifndef when you want to compile a section only if a specified expression has not been defined.
You would need to use $IF instead:
{$IF Defined(Condition1) or Defined(Condition2)} DoSomething; {$IFEND} In case you have to support old Delphis (without the support for the $IF metadirective), you can use one simple and one ugly workaround:
//AND {$IFDEF Cond1}{$IFDEF Cond2}DoSomething{$ENDIF}{$ENDIF} //OR {$UNDEF Cond1OrCond2} {$IFDEF Cond1}{$DEFINE Cond1OrCond2}{$ENDIF} {$IFDEF Cond2}{$DEFINE Cond1OrCond2}{$ENDIF} {$IFDEF Cond1OrCond2}DoSomething{$ENDIF} If you are repeating the test more than once, first case should be rewritten as follows.
{$UNDEF Cond1AndCond2} {$IFDEF Cond1}{$IFDEF Cond2}{$DEFINE Cond1AndCond2{$ENDIF}{$ENDIF} {$IFDEF Cond1AndCond2}DoSomething{$ENDIF} If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
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