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Is integer overflow defined in VHDL?

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I was wondering if integer overflow is defined in VHDL. I wasn't able to find anything in the 2002 Specification.

As an example (Note, this might not compile, it's just a generic example...):

entity foo is port (
    clk : std_logic
);
end entity;

architecture rtl of foo is
    signal x : integer range 0 to 2 := 0;
begin
    process (clk)
    begin
        if rising_edge(clk) then
            x <= x + 1;
        end if;
    end process;
end architecture;

It's clear that x will go from 0 to 1, and then to 2. Is it defined what will happen on the next increment? Is that undefined behavior?