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New posts in x86

Intel's CLWB instruction invalidating cache lines

How do I store the value of a register into a memory location pointed to by a pointer?

c++ pointers assembly x86

Recreate dead threads after a fork

c linux 64-bit x86 fork

Performance difference between system call vs function call

Atomic Minimum on x86 using OpenMP

c++ x86 openmp atomic minimum

Can a shift using the CL register result in a partial register stall?

Why is protected mode needed in addition to compatibility mode in Intel x86 64 bit CPUs?

x86 cpu x86-64 protected-mode

How to merge a scalar into a vector without the compiler wasting an instruction zeroing upper elements? Design limitation in Intel's intrinsics?

c gcc x86 sse intrinsics

Best way to load/store from/to general purpose registers to/from xmm/ymm register

assembly x86 simd sse2 avx2

Can PTEST be used to test if two registers are both zero or some other condition?

assembly x86 sse intrinsics sse4

Jump back some iterations for vectorized remainder loop

c performance assembly x86 simd

Can two different objects with automatic storage duration compare equal under address comparison?

c x86 clang

Are write-combining buffers used for normal writes to WB memory regions on Intel?

x86 BSWAP instruction REX doesn't follow Intel specs?

libc's system() when the stack pointer is not 16-padded causes segmentation fault

Difficulty understanding logic in disassembled binary bomb phase 3

How to explicitly load a structure into L1d cache?

Is there a way for a kernel module to find section addresses of another loaded module?

Faster assembly optimized way to convert between RGB8 and RGB32 image

Why does switch_to use push+jmp+ret to change EIP, instead of jmp directly?

assembly linux-kernel x86