Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in x86

AVX2 VPSHUFB emulation in AVX

x86 simd intrinsics avx

What comes after QWORD?

assembly x86 intel terminology

What does F in FWORD stand for?

assembly x86 definition word low-level

Creating a C function without compiler generated prologue/epilogue & RET instruction?

c gcc assembly x86 nasm

Does a hyper-threaded core share MMU and TLB?

x86 cpu-architecture tlb mmu hyperthreading

Difference between .dynamic .dynsym and .dynstr in an ELF executable

linux x86 elf

How do the store buffer and Line Fill Buffer interact with each other?

x86 cpu-architecture cpu-cache micro-architecture cpu-mds

Integer Overflow problem

assembly x86

_mm_alignr_epi8 (PALIGNR) equivalent in AVX2

x86 simd intrinsics avx avx2

How to make a Makefile for a program for assembly Language?

linux assembly makefile x86 nasm

What will be used for data exchange between threads are executing on one Core with HT?

multithreading concurrency x86 x86-64 hyperthreading

Function parameter passing in a Linux kernel interrupt handler (from asm to C)

assembly linux-kernel x86 interrupt-handling calling-convention

Using db to declare a string in assembly NASM

string assembly x86 nasm bootloader

Registering Interrupt in 16 bit x86 Assembly

assembly x86 nasm interrupt x86-16

Is `reinterpret_cast`ing between hardware SIMD vector pointer and the corresponding type an undefined behavior?

c++ x86 language-lawyer undefined-behavior intrinsics

(meaningful) cost of the jump instruction?

assembly x86

What happens when a rep-prefix is attached to a non string instruction?

string assembly x86 undefined-behavior

How to use the APIC to create IPIs to wake the APs for SMP in x86 assembly?

assembly x86 intel smp

Why does x86 architecture use two stack registers (esp ; ebp)?

assembly x86 x86-64

Does using mix of pxor and xorps affect performance?

assembly x86 sse simd
« Newer Entries Older Entries »