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New posts in x86

Does the MOV x86 instruction implement a C++11 memory_order_release atomic store?

c++ c++11 x86 memory-model stdatomic

Fast byte-wise replace if

c optimization x86 sse simd

How are dw and dd different from db directives for strings?

string assembly x86 nasm masm

What's the easiest way to determine if a register's value is equal to zero or not?

assembly x86 micro-optimization

Difference between "or eax,eax" and "test eax,eax" [duplicate]

assembly x86 micro-optimization

Popcount of SSE vectors for binary correlation?

performance optimization x86 bit-manipulation sse

Reference material for uops?

x86 cpu intel cpu-architecture

Packing BCD to DPD: How to improve this amd64 assembly routine?

performance assembly x86 bcd dpd

What is the significance of operations on the register EAX having their own opcodes?

assembly x86 machine-code instructions opcode

Memory Model in C++ : sequential consistency and atomicity

c++ multithreading c++11 x86 stdatomic

What exactly happens when a skylake CPU mispredicts a branch?

x86 intel cpu-architecture branch-prediction speculative-execution

Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?

performance assembly x86 intel micro-optimization

In which condition DCU prefetcher start prefetching?

x86 intel cpu-architecture cpu-cache prefetch

sys_execve system call from Assembly

linux assembly x86 system-calls

What does alignment to 16-byte boundary mean in x86

optimization x86 memory-alignment

What is an assembly-level representation of pushl/popl %esp?

assembly x86 stack-memory instruction-set stack-pointer

Why does switching from AT&T to Intel syntax make this tutorial segfault using GAS?

assembly x86 intel gnu-assembler att

Is it possible to run 16 bit code in an operating system that supports Intel IA-32e mode?

x86 kernel x86-64 cpu

How can you insert a NaN into a xmm register?

assembly x86 nan sse

Online Assembly language resources [closed]

visual-c++ assembly x86
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