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New posts in x86-64
Linux x86_64 assembly socket programming
Sep 14, 2022
intel
c
linux
sockets
assembly
x86-64
Assembly - inline asm - copy from one array to another?
Dec 06, 2018
intel
linux
assembly
x86-64
cpu-registers
att
Can I use some bits of pointer (x86_64) for custom data? And how if possible?
Jul 13, 2022
intel
pointers
x86-64
How to get this simple assembly to run?
Aug 31, 2022
intel
macos
assembly
linker
x86-64
nasm
error in backend: 32-bit absolute addressing is not supported in 64-bit mode
Apr 13, 2022
intel
macos
assembly
x86-64
intel-syntax
find address of PLT stub
Mar 04, 2022
intel
linux
x86-64
elf
plt
got
Is the stack frame required for all functions in C on x86-64?
Mar 31, 2022
intel
c
assembly
x86
stack
x86-64
Is the Microsoft Stack always aligned to 16-bytes?
Nov 09, 2022
intel
windows
assembly
stack
x86-64
calling-convention
What is practical application of x86 RCL/RCR instructions?
Mar 25, 2022
intel
assembly
x86
bit-manipulation
x86-64
bit-shift
Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
Apr 16, 2022
intel
x86
x86-64
cpu
cpu-architecture
Why would one use "ret" instead of "call" to call a method?
Sep 10, 2022
intel
assembly
x86-64
osdev
spectre
Why doesn't the same generated assembler code lead to the same output?
Jun 06, 2022
intel
c
floating-point
x86-64
floating-accuracy
icc
Self-modifying code sees a 0xCC byte but the debugger doesn't show it?
Mar 06, 2016
assembly
gdb
x86-64
breakpoints
self-modifying
intel
How to execute a call instruction with a 64-bit absolute address?
Feb 07, 2022
assembly
x86-64
nasm
jit
function-call
Was there a P4 model with double-pumped 64-bit operations?
Apr 25, 2022
x86
x86-64
intel
cpu-architecture
Can rip be used with another register with RIP-relative addressing?
Nov 09, 2022
assembly
x86-64
addressing-mode
UEFI boot services CreateEvent() returning status EFI_INVALID_PARAMETER
Sep 15, 2022
assembly
x86
x86-64
nasm
uefi
g++ Optimization Flags: -fuse-linker-plugin vs -fwhole-program
Oct 19, 2022
intel
c++
linux
g++
x86-64
ld
Performance implications of context switches for 64-bit segment bases
May 17, 2020
intel
c
linux
performance
x86-64
cpu-registers
Do all 64 bit intel architectures support SSSE3/SSE4.1/SSE4.2 instructions?
Sep 09, 2022
intel
x86-64
cpu-architecture
simd
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