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New posts in intel

VirtualBox - Kernel requires an x86-64 cpu but only detected an i686 cpu

virtualbox x86-64 intel ubuntu-14.04

Is the Intel Xeon Phi usable without a costly Intel Compiler?

compiler-construction parallel-processing hardware intel intel-mic

Strange JIT pessimization of a loop idiom

java cpu intel microbenchmark jmh

Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?

performance assembly x86 intel

Android emulator system images and AMD processor

android android-emulator arm mips intel

Enabling floating point interrupts on Mac OS X Intel

macos intel interrupt floating-point-exceptions

What are "non-virtualizable" instructions in x86 architecture?

x86 intel virtualization computer-architecture xen

Understanding %rip register in intel assembly

assembly x86-64 intel mov addressing-mode

Why did Intel change the static branch prediction mechanism over these years?

x86 compiler-construction intel cpu-architecture branch-prediction

How are the gather instructions in AVX2 implemented?

intel ram simd avx avx2

How many instructions are there on x86 today? [closed]

assembly x86 64-bit intel amd-processor

How do Intel Xeon CPUs write to memory?

caching optimization x86 intel cpu-cache

How much should I worry about the Intel C++ compiler emitting suboptimal code for AMD?

c++ optimization compiler-construction intel amd-processor

Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs

performance assembly x86 intel micro-optimization

How to read the Intel Opcode notation

assembly x86 intel opcode machine-code

Is double read atomic on an Intel architecture?

c# .net intel

What is the latency and throughput of the RDRAND instruction on Ivy Bridge?

assembly intel rdrand

Can one construct a "good" hash function using CRC32C as a base?

hash intel sse crc32

What is the purpose of CS and IP registers in Intel 8086 assembly?

x86 intel x86-16

ASM: MASM, NASM, FASM?

assembly intel nasm masm fasm
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