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New posts in cpu-architecture

Are correct branch predictions free?

cpu cpu-architecture

What are shadow registers in MIPS and how are they used?

mips cpu cpu-registers cpu-architecture

Is memory outside each core always conceptually flat/uniform/synchronous in a multiprocessor system?

memory cpu-architecture cpu-registers cpu-cache memory-barriers

Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?

intel x86 x86-64 cpu cpu-architecture

Why does 20 address space with on a 16 bit machine give access to 1 Megabyte and not 2 Megabytes?

memory cpu-architecture x86-16 memory-address processor

What does the processor do while waiting for a main memory fetch

cpu cpu-architecture cpu-cache

Updating page table when an entry is evicted from TLB

operating-system cpu-architecture virtual-memory tlb page-tables

Was there a P4 model with double-pumped 64-bit operations?

x86 x86-64 intel cpu-architecture

Can a load or store be reordered before a conditional?

c++ concurrency language-lawyer cpu-architecture lock-free

Do store instructions block subsequent instructions on a cache miss?

c++ concurrency x86 cpu-architecture cpu-cache

Does it cost significant resources for a modern CPU to keep flags updated?

performance assembly cpu-architecture micro-optimization eflags

Can two fuseable pairs be decoded in the same clock cycle?

assembly x86 cpu intel cpu-architecture

Which architecture to call Non-uniform memory access (NUMA)?

cpu intel cpu-architecture numa

Why does the 80x87 instruction set use a "stack-based" design?

assembly x86 cpu-architecture instruction-set x87

When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation?

cpu-architecture cpu-cache mmu page-tables

Conflict Miss v/s Compulsory Miss

caching memory-management cpu-architecture

CPU cache: does the distance between two address needs to be smaller than 8 bytes to have cache advantage?

caching cpu-architecture cpu-cache

Exactly how "fast" are modern CPUs?

intel performance assembly x86 cpu-architecture cpu-speed

Do all 64 bit intel architectures support SSSE3/SSE4.1/SSE4.2 instructions?

intel x86-64 cpu-architecture simd

Critical sections with multicore processors

multithreading synchronization cpu-architecture
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