Include in Makefile another Makefile with relative path

Question

I have a directory tree like this with some "shared targets" in the file rules.Makefile:

├── Makefile
├── rules.Makefile
└── my_subdir
    └── Makefile

I would like to invoke these "shared targets" in both the Makefile(s) in the parent directory and the child directory.

Also the "custom targets" in the Makefile in the child directory should be callable from the Makefile in the parent directory.

For some reason I am able to call the targets in rules.Makefile only from the sibling Makefile (the one in the parent directory). When using relative paths in the Makefile in the child directory trying to access the rules.Makefile in the parent directory I get some errors.

The content of the Makefile in the parent directory:

RULES_MAKEFILE_PATH=$(PWD)/rules.Makefile
include $(RULES_MAKEFILE_PATH)

foo-parent:
    @echo $(RULES_MAKEFILE_PATH)

The content of the Makefile in the child directory (please note that double dot ..):

RULES_MAKEFILE_PATH=$(PWD)/../rules.Makefile
include "$(RULES_MAKEFILE_PATH)"

foo-child:
    @echo $(RULES_MAKEFILE_PATH)

When calling from the parent directory make foo-parent then I see the expected path.

When calling from the child directyr make foo-child then I see this error:

$ make foo-child 
Makefile:9: "/<PARENT_PATH>/my_subdir/../rules.Makefile": No such file or directory
make: *** No rule to make target '"/<PARENT_PATH>/my_subdir/../rules.Makefile"'. Stop.

• How can I make the relative paths work in the "child directory"?
• Also how can I call the targets defined in the Makefile in child directory (e.g. foo-child) from the Makefile in the parent directory?

Answer 1

Well first, $(PWD) is not a special variable to make. It's just a normal variable, that's imported from your shell. So it will always have the same value everywhere in your makefile and in all included makefiles, it won't change just because you're including a makefile from a different directory.

Second, even for $(CURDIR) (which is a special variable and is set by make to be the current directory when make starts), it is never reset when you include a makefile from another directory.

And, all paths in include lines are evaluated based on the directory make was in when it started, not on a path relative to the currently-parsed makefile. So if Makefile includes foo/Makefile, then foo/Makefile has an include bar.mk, make will look for bar.mk not foo/bar.mk.

Answer 2

The point about $(PWD) above is true. However, if that is not a concern, you could still use the shell function to execute commands to get paths of another Makefile to include: $(shell pwd)

I did something similar for a project that benefited from having the same Makefile used in many places, using git rev-parse --show-toplevel.

MAKEFILE := $(shell git rev-parse --show-toplevel)/makefiles/example.def
include $(MAKEFILE)