How to receive L1, L2 & L3 cache size using CPUID instruction in x86

Question

I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size.

I tried to find something in Intel Documentation & in the Internet but I failed.

THE MAIN PROBLEM IS: In case of AMD processors it is just to set EAX register to 80000005h & 80000006h values and get desired data from ECX and EDX registers but in case of Intel I can obtain this information only for L2.

What should I do to get L1 & L3 cache size for Intel processors ?

Answer 1

Marat Dukhan basically gave you the right answer. For newer Intel processors, meaning those made in the last 5-6 years, the best solution is to enumerate over the cpuid leaf 4, meaning you call cpuid a few times, first with EAX=4 and ECX=0, then with EAX=4 and ECX=1 and so forth. This will return info not only on the cache sizes and types but also tell you how these caches are connected to the CPU cores and hyperthreading/SMT units. The algorithm and sample code is given at https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ , more specifically in the section titled "Cache Topology Enumeration".