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How to get the size of the CPU cache in Linux

I have executed the following query:

free -m

And output of this command is:

           total       used       free     shared    buffers     cached
Mem:        2048       2018         29          5          0       595

I want to get the size of the CPU cache. Is it possible to get the size of the cache and also what is the use of the cache here?

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Naveen Kumar Mishra Avatar asked May 13 '15 06:05

Naveen Kumar Mishra


People also ask

How do I see cache size in Linux?

The CPUID x86 instruction also offers cache information, and can be directly accessed by userland. ARM also has an architecture-defined mechanism to find cache sizes through registers such as the Cache Size ID Register (CCSIDR), see the ARMv8 Programmers' Manual 11.6 "Cache discovery" for an overview.

How do I check my CPU cache size?

Right-click on the Start button and click on Task Manager. 2. On the Task Manager screen, click on the Performance tab > click on CPU in the left pane. In the right-pane, you will see L1, L2 and L3 Cache sizes listed under “Virtualization” section.

What is the size of L1 cache?

There are 4 cores reported, then the total size of L1 cache = 4 X 64 KB = 256 KB.

How large is a cache line?

The cache line is generally fixed in size, typically ranging from 16 to 256 bytes. The effectiveness of the line size depends on the application, and cache circuits may be configurable to a different line size by the system designer.


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2 Answers

If you want to get the size of the CPU caches in Linux, the easiest way to do that is lscpu:

$ lscpu | grep cache
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              15360K

If you want to get detailed information on each cache, check the sysfs file system:

$ SYSNODE=/sys/devices/system/node
$ grep '.*' $SYSNODE/node*/cpu*/cache/index*/* 2>/dev/null | 
    awk '-F[:/]' '{ printf "%6s %6s %24s %s\n" $6, $7, $9, $10, $11 ; }'
node0  cpu0 index0                    level 1
node0  cpu0 index0           number_of_sets 64
node0  cpu0 index0  physical_line_partition 1
node0  cpu0 index0          shared_cpu_list 0,12
node0  cpu0 index0           shared_cpu_map 0000,00001001
node0  cpu0 index0                     size 32K
node0  cpu0 index0                     type Data
node0  cpu0 index0    ways_of_associativity 8
node0  cpu0 index1      coherency_line_size 64

Some cache instances will be seen multiple times (per each hardware thread), but you can check that in the shared_cpu_list field.

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myaut Avatar answered Oct 19 '22 23:10

myaut


getconf

getconf -a | grep CACHE

gives:

LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  262144
LEVEL2_CACHE_ASSOC                 8
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  20971520
LEVEL3_CACHE_ASSOC                 20
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

Or for a single level:

getconf LEVEL2_CACHE_SIZE

The cool thing about this interface is that it is just a wrapper around the POSIX sysconf C function (cache arguments are non-POSIX extensions), and so it can be used from C code as well:

long l2 = sysconf(_SC_LEVEL2_CACHE_SIZE);

Tested on Ubuntu 16.04 (Xenial Xerus).

x86 CPUID instruction

The CPUID x86 instruction also offers cache information, and can be directly accessed by userland.

glibc seems to use that method for x86. I haven't confirmed by step debugging / instruction tracing, but the source for 2.28 sysdeps/x86/cacheinfo.c does that:

__cpuid (2, eax, ebx, ecx, edx);

TODO: Create a minimal C example, lazy now, asked at: How to receive L1, L2 & L3 cache size using CPUID instruction in x86

ARM also has an architecture-defined mechanism to find cache sizes through registers such as the Cache Size ID Register (CCSIDR), see the ARMv8 Programmers' Manual 11.6 "Cache discovery" for an overview.