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I have a C++ preprocessor written like this:
#ifdef cpp_variable //x+y; #endif Can anyone tell me how to define this in Makefile.
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A macro is a variable that MAKE expands into a string whenever MAKE encounters the macro in a makefile. For example, you can define a macro called LIBNAME , which represents the string mylib. lib . To do this, type the line LIBNAME = mylib. lib at the beginning of your makefile.
CPPFLAGS. CPPFLAGS is used to pass extra flags to the C preprocessor. These flags are also used by any programs that use the C preprocessor, including the C, C++, and Fortran compilers. You do not need to explicitly call the C preprocessor.
This is compiler specific.
GCC uses -Dcpp_variable=VALUE or just -Dcpp_variable
Microsoft's compilers use /D
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