How to declare output array in VHDL?

Question

In VHDL how we can declare output array. I know to how to declare a signal as array, by first declaring the type and then defining a signal as this type. Is it possible to do same on output?

Answer 1

If you want to declare a new type of an array for use on module output, thus not use some existing array type like std_logic_vector, then the type must be declared in a package, in order to make the type available where the module is instantiated. Example below:

library ieee;
use ieee.std_logic_1164.all;

package pkg is
  type slv8_array_t is array (natural range <>) of std_logic_vector(7 downto 0);
end package;

package body pkg is
end package body;


library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg.all;

entity mdl is
  port(
    array_o : out slv8_array_t(0 to 3));
end entity;

architecture syn of mdl is
begin
  array_o <= (others => (others => '0'));
end architecture;

A similar approach applies to other declared types, like for example records, or for other kind of interface type sharing like input.