how to compile a kernel module

Question

I'm trying to compile a simple hello world module following this guide and I'm confused about what the Makefile is actually doing.

obj-m += hello-1.o

all:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

clean:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

I understand that when i type the make command it will run the all recipe which runs make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules. So now it runs the Makefile found at the path given after the -C flag but what does the M=$(PWD) modules do?

Answer 1

1. 'obj-m' :- specifies object files which are built as loadable kernel modules.

2. 'all and clean' :- If you run 'make' by default it will run "all :". But we can use all and clean with make. it will run only those specific command.

   Example :-
           'make all' will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules"
           'make clean will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean"
   

3.'uname -r' :- get name and information about current kernel.

 Example :- for me, my kernel is "4.6.0-rc1".

4. Option ‘-C dir’ :- Change to directory dir before reading the makefiles.

   Example :- "make -C /lib/modules/$(shell uname -r)/build" will change to "make -C /lib/modules/4.6.0-rc1/build.
   

5. '$pwd':- get the path of your current directory.

Now you want to create your loadable module by using "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules".

Your source code need environment to run. That's why we have to use -C option to change build directory. Which have all needed definition, header file, Macro and etc. Now after changing to build directory you need to tell where is your module present, that's why we are using M=$PWD.