How to build multiple targets from one makefile

Question

I'm trying to parameterize my makefile targets. Currently, it has a

TARGET = main

declaration near the top. It derives the SRC list from that as well as does lots of other things.

I've changed my C code though, so that I have multiple different top level .c files to basically get variant builds. So what I want to be able to do is basically do

make target1

or

make target2

And vary what TARGET is set to in the makefile. I'm confused how to accomplish this. I thought I might add something like

target1: all
    TARGET=target1

This didn't seem to work too well at all though. Is there a general pattern for how one does this?

Answer 1

I would suggest simply spelling out your targets as separate targets in the makefile:

all: target1 target2

OTHER_OBJS = misca.o miscb.o miscc.o

target1: target1.o $(OTHER_OBJS)

target2: target2.o $(OTHER_OBJS)

Then make, make target1, make target2, and so on will all do what you want.

You say your makefile "derives the SRC list from [$(TARGET)]" in some presumably high-tech way, but it might be interesting to try explicitly listing the object files in a low-tech way instead, as above. Using different make targets is arguably Make's general pattern for producing different results.

Answer 2

Parameterized variable names and target-specific variables may do what you want, as the value of a target-specific variable is normally "inherited" by the prereqs of that target (assuming you are using GNU make):

target1_SRC=123 456
target2_SRC=abc def

target1: TARGET=target1
target2: TARGET=target2

target1: all
target2: all

all: ; @echo $($(TARGET)_SRC)

Then you can run make target1 or make target2, for example:

$ make target1
123 456
$ make target2
abc def