How is the x64 architecture different from x86

Question

I need to mess around with the stacks on these architecture and am really a n00b here. Any pointers to reading topics/google searches that i can do. I am looking for how these architectures are fundamentally different from each other. something more than the wikipedia article on this topic http://en.wikipedia.org/wiki/X64

Answer 1

In x86 there are 8 32 bit registers, in x64 the registers are 64 bits each and there are 8 more of them. The 128 bit SSE registers are 128 bits in both, but on x86 there are 8 of them while in x64 there are 16 of them. Also some instructions were cut in x64.

In x64 mode you can still use the registers as 32 bits by using their 32 bit name(starting with an 'e') instead of their 64 bit name(starting with an 'r'), and the assembly would be mostly the same.

http://en.wikipedia.org/wiki/X86#x86_registers

Or if you want some really heavy reading(like 1000s of pages...)

http://www.intel.com/products/processor/manuals/index.htm I read through a few hundred pages of those manuals and learned a lot, really good stuff.

Answer 2

All the answers here mention the changes in the register set, which I'll list here for completeness:

• All existing 32-bit general purpose registers are extended to 64 bits (EAX is extended to RAX and so on)
• 8 new 64-bit general purpose registers (R8 through R15)
• 8 new 128-bit SSE registers (XMM8 through XMM15)

There are also changes in addressing modes:

• CS, DS, ES and SS are flat. That is, their base is 0x0 and their limit is 0xffffffffffffffff. FS and GS can have a base over 32 bits.
• Descriptors in the GDT, LDT and IDT have changed. They have 8 bytes in 64-bit mode
• A non-contiguous address space. In 32-bit mode the linear address space is from 0x0 to 0xfffffff. In 64-bit mode the linear address space is split from 0x0 to 0x00007ffffffff and from 0xffff800000000000 to 0xffffffffffffffff. Basically, there are only 48 bits of address, and the address is sign-extended to 64 bits.
• A new paging mode.

Various instructions were removed:

• One byte INC instructions with encoding 40+rw and 40+rd. The 4x byte became the REX prefix.
• instructions for loading the segment registers that are now flat: LDS, LDS, LSS.

There are more differences that I simply can remember off the top of my head. I'll add them if I can think of some more.