How does 'alignment of memory operands' help MIPS to be pipelined?

Question

How does 'alignment of memory operands' help MIPS to be pipelined?

The book says:

Fourth, as discussed in Chapter 2, operands must be aligned in memory. Hence, we need not worry about a single data transfer instruction requiring two data memory accesses; the requested data can be transferred between processor and memory in a single pipeline stage.

I think I understand that one data transfer instruction does not require two or more data memory aaccesses. However, I am not sure what does it have to do with the alignment of memory operands.

Thanks, in advance!

Answer 1

The lw instruction requires that the memory address be word aligned.

Therefore, to access an unaligned word, one would need to access the two word boundaries that the required word intersects and mask out the necessary bytes.

For example, suppose you desire to load a word stored at address 0x2. 0x2 is not word aligned, so you would need to load the half word stored at 0x2 and the half-word stored at 0x4.

To do so, one might write:

lh  $t0 2($zero)
lh  $t1 4($zero)
sll $t1 $t1 16
or  $t2 $t0 $t1

This only gets more complicated if you want to load for example a word stored at address 0x3:

# load first byte
lb  $t0 3($zero)

# load second word, mask out first 3 bytes
lw  $t1 4($zero)
lui $t2 0x0000FFFF
ori $t2 $t2 0xFFFFFFFF
or  $t1 $t1 $t2

# combine
sll $t1 $t1 8
or  $t2 $t0 $t1

So, it can be seen that the requirement for word alignment doesn't help MIPS to be pipelined, but rather that access to unaligned words requires excess memory accesses — this is a limitation of the ISA.