How do you initialize a parameter array in Verilog

Question

This gives me an error saying that I can't assign a packed type to an unpacked type. I agree that the right side is an array of packed types, but why is the left side of the expression an unpacked type?

parameter [7:0] lsfr_taps [0 : 7]   = {8'd9, 8'd5, 8'd3, 8'h21, 8'd9, 8'd9, 8'd5, 8'd9};

Regardless the more important question is how do I inialize a two-dimensional array of multi-bit parameters in Verilog?

Answer 1

Your initialisation is fine. You just need to add a ' before {:

parameter [7:0] lsfr_taps [0 : 7]   = '{8'd9, 8'd5, 8'd3, 8'h21, 8'd9, 8'd9, 8'd5, 8'd9};