$ cat Makefile
all:
echo VAR is ${HOME}
echo VAR is $${HOME}
Gives
$ make
echo VAR is /home/abc
VAR is /home/abc
echo VAR is ${HOME}
VAR is /home/abc
Why does echo VAR is ${HOME}
syntax work in Makefile? I thought, to use shell variables you have to use $${HOME}}
And in your scenario, $MAKE is used in commands part (recipe) of makefile. It means whenever there is a change in dependency, make executes the command make --no-print-directory post-build in whichever directory you are on.
You can use shell function: current_dir = $(shell pwd) . Or shell in combination with notdir , if you need not absolute path: current_dir = $(notdir $(shell pwd)) .
A simple makefile consists of "rules" with the following shape: target ... : dependencies ... command ... ... A target is usually the name of a file that is generated by a program; examples of targets are executable or object files.
Yes and no. It is best to use $$
to be explicit. However, there is a special rule for environment variables:
Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. But an explicit assignment in the makefile, or with a command argument, overrides the environment. (If the `-e' flag is specified, then values from the environment override assignments in the makefile. See section Summary of Options. But this is not recommended practice.)
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