I have a project that has a makefile with broken dependencies. Is there any best known way to generate a list of dependencies for the project that I can use in the makefile, other than examining each source file by hand or with a hand written perl script?
Makefile is a set of commands (similar to terminal commands) with variable names and targets to create object file and to remove them. In a single make file we can create multiple targets to compile and to remove object, binary files. You can compile your project (program) any number of times by using Makefile.
A dependency is a file that is used as input to create the target. A target often depends on several files. A command is an action that make carries out. A rule may have more than one command, each on its own line.
make is a command/program that enacts builds according to a dependency graph expressed in a makefile.
Makefile sets a set of rules to determine which parts of a program need to be recompile, and issues command to recompile them. Makefile is a way of automating software building procedure and other complex tasks with dependencies. Makefile contains: dependency rules, macros and suffix(or implicit) rules.
GNU make's documentation provides a good solution.
Absolutely. g++ -MM <your file>
will generate a GMake compatible list of dependencies. I use something like this:
# Add .d to Make's recognized suffixes. SUFFIXES += .d #We don't need to clean up when we're making these targets NODEPS:=clean tags svn #Find all the C++ files in the src/ directory SOURCES:=$(shell find src/ -name "*.cpp") #These are the dependency files, which make will clean up after it creates them DEPFILES:=$(patsubst %.cpp,%.d,$(SOURCES)) #Don't create dependencies when we're cleaning, for instance ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) #Chances are, these files don't exist. GMake will create them and #clean up automatically afterwards -include $(DEPFILES) endif #This is the rule for creating the dependency files src/%.d: src/%.cpp $(CXX) $(CXXFLAGS) -MM -MT '$(patsubst src/%.cpp,obj/%.o,$<)' $< -MF $@ #This rule does the compilation obj/%.o: src/%.cpp src/%.d src/%.h @$(MKDIR) $(dir $@) $(CXX) $(CXXFLAGS) -o $@ -c $<
Note: $(CXX)
/gcc
command must be preceded with a hard tab
What this will do is automatically generate the dependencies for each file that has changed, and compile them according to whatever rule you have in place. This allows me to just dump new files into the src/
directory, and have them compiled automatically, dependencies and all.
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