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I have a third party makefile, and I'd like one of the targets (T1) to not be built until another, custom target (T2) is built first. Normally, this would be accomplished by making T2 a prerequisite of T1. BUT, T1 uses the $^ in one of its rules.. so, by adding the prerequisite, I end up breaking the build... What I have is this:
T1: x y z T2
$(MAKE) -j $^;
# fails because T2 should not be passed to the make!!!
.PHONY: T2
T2:
#do some linking and prep for T1
Is there a good way to ensure that T2 is run before T1? (Note: the above example is actually simplified by a bit. T1 is actually the vmlinux target within the Linux kernel makefile, so rewriting it is not only difficult, it makes the code non-portable. Also, I can't run T2 before calling make on the kernel due to some other dependencies).
776
The order of rules is not significant, except for determining the default goal : the target for make to consider, if you do not otherwise specify one. The default goal is the target of the first rule in the first makefile. If the first rule has multiple targets, only the first target is taken as the default.
Order-only prerequisites is not about the order in which they are processed. They can be processed in any order, and can be processed even in parallel. Order-only means that updating prerequisite doesn't make updating the target.
Basically, the prerequisites in Makefile have two functions: They are checked and, if necessary, are built before the target. If any of the prerequisites gets rebuilt (or is simply newer than the target) then the target will also be rebuilt.
Have T2 as an order-only prerequisite:
T1: x y z | T2
$(MAKE) -j $^;
# Make will run the T2 rule before this one, but T2 will not appear in $^
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