FFT implementation in Verilog : Error using nested for loop

Question

This post is related to the my previous post related to FFT.

FFT implemetation in Verilog: Assigning Wire input to Register type array

I want to assign output of first stage to input of second stage of FFT butterfly modules. I have to re-order the output of first stage according to input of second stage. Here is my code to implement the swapping.

always@ (posedge y_ndd[0] or posedge J)
begin

if(J==1'b1)
begin
    for (idx=0; idx<N/2; idx=idx+1)
     begin
         IN[2*idx] <= X[idx*2*X_WDTH+: 2*X_WDTH];
         IN[2*idx+1] <= X[(idx+N/2)*2*X_WDTH+: 2*X_WDTH];
     end
end

else
begin
    level=level+1;
    modulecount=0;
    for(jj=0;jj<N;jj=jj+(2**(level+1)))
        begin
        for (jx=jj; jx<jj+(2**level); jx=jx+1)//jj+(2**level)
         begin
             IN[modulecount] <=OUT[jx];
             IN[modulecount+1] <=OUT[jx+(2**level)];
             modulecount=modulecount+1;
         end
        end
end

end

When I synthesize this, It gives 2 errors.

ERROR:Xst:891 - "Network.v" line 161: For Statement is only supported when the new step evaluation is constant increment or decrement of the loop variable.
ERROR:Xst:2634 - "Network.v" line 161: For loop stop condition should depend on loop variable or be static. 

Can't we use non-constant increment and non-static stop coditions?

If that so, how we handle this.

Any help is appreciated. Thanks in advance.

Answer 1

Synthesis tools unroll loops in order to synthesize the circuit. Therefore, only loops that iterate a constant number of times, whose constant is known at compile/elaboration time are synthetisable.

When the stop value is not known, you can assume a maximum number of iterations and use that as the stop condition. Then add the original stop condition as a conditional statement inside the loop:

        for (jx=jj; jx < MAX_LOOP_ITERATION; jx=jx+1)//jj+(2**level)
         begin
           if (jx<jj+(2**level))   // <---------- Add stop condition here
           begin
             IN[modulecount] <=OUT[jx];
             IN[modulecount+1] <=OUT[jx+(2**level)];
             modulecount=modulecount+1;
           end
         end

If N is not a constant, the outer loop should also be fixed using a similar conditional statement. You also need to fix the increment value and each time add a constant value. Use a conditional statement to check if jj==jj+(2**(level+1))

Obviously, you need to be careful as a high max number may increase your worst case delay and the minimum clock cycle time.