Does anyone know what is ERG on Apple's A5, A5X, A6 and A6X processors?
We ran into an obscure bug with LDREX/STREX instructions and the behavior is different between A5's and A6's. The only explanation I have is that they have different ERG, but can't find anything on that. I also could not find a way to retrieve this value, the MRC instruction seems to be prohibited in the user mode on iOS.
Thank you!
On OMAP 4460 (ARM Cortex-A9, same as Apple A5/A5X) ERG is 32 bytes (which is same as cache line size).
I don't know that those values are on A6/A6X (and there is no way to find out without loading your own driver, which you can not do on Apple devices), but my guestimate is that cache line size increased to 64 bytes, and so did ERG.
Alternatively, you may optimize the algorithm for the architectural maximum of 512 words (2K bytes).
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With