Echo in makefile

Question

Trying to find simple way of printing information in makefile. At the bottom is shown my simple makefile.

Line $(info aaa) prints aaa fine. But line echo 'aaa' creates error *** missing separator

Is it possible to print info using echo in makefile?

CC=gcc
CFLAGS=-I.
DEPS = f1.h,hellomake.h

echo 'aaa'
$(info aaa)

%.o: %.c $(DEPS)
        $(CC) -c -o $@ $< $(CFLAGS)

hellomake: hellomake.o hellofunc.o f1.o 
        gcc -o hellomake hellomake.o hellofunc.o f1.o -I.

Answer 1

You can use trick like this in your Makefile:

a = $(shell echo abc)
$(info $(a))

Answer 2

Makefiles are not executed line by line, but regarding the rule dependencies. Your echo statement does not belong to a rule, but make thinks it should, thus the error message.

If you want to generate a general output independent of any dependency, $(info ...) (or $(warning ...)) is the way to go.