How to add #define in Makefile?

Question

I have a c++ project in which i need to define a variable in some CXX files. I have nearly 800 files out of which i need to define a variable for 200 files. So i was thinking to define it in makefile. So how can we do that.

Answer 1

Just add -Dxxx=yy on the command line (xxx the name of the macro and yy the replacement, or just -Dxxx if there is no value).

It's not a Makefile command, it's part of the compiler command line options.

Answer 2

Let's say you want a replacement for #define MYDEF

In your makefile you have the compiler command line, something like (simplest example):

g++ -o myfile.cpp

To get that #define for every myfile.cpp just use -D like so:

g++ -DMYDEF -o myfile.cpp