Do we ever need memory barriers with C++ atomics on Intel x86?

Question

I thought only string and (certain) streaming instructions require memory barriers on Intel x86? For all other instructions the Intel strong memory ordering model ensures that consistency is achieved?

Assuming the above is correct, why do we need to use C++ atomics (excluding compare-and-exchange) when our code is only executing on Intel x86?

I really am getting myself confused where we need to use atomics and whether using atomics inhibits the out-of-order-execution due to memory barriers and then the whole MESI protocol.

MESI just ensures the caches are consistent across all processors?

Memory barriers are useful on other architectures because they flush the CPU store buffers to the caches, to allow MESI to ensure consistency?

When do we need to use atomics on Intel X86 CPUs?

Answer 1

While X86 is cache-coherent, it doesn't mean it gives you the guarantees you expect to find. There are different instructions for atomic save and regular save and they behave differently. Also, and equally importantly, atomic variables prevent 'destructive' compiler optimizations. Without those, the compiler will easily optimize your code according to single-threaded execution model, and your programm will misbehave.