Controlling verbosity of make

Question

I'm using a makefile to compile a program made of many .c files, and any time make is invoked it only compiles those files modified after the last run (nothing special until here).

To avoid cluttering my screen, I prepend @ at the beginning of each $(CC) call, and before it I print a customized echo message. For example:

%.o: %.c $(h1) $(h3) %.h
    @echo -e "\tCompiling <" $< 
    @$(CC) $(CFLAGS) -c $< -o $(libDir)$@$(MATHOPTS)

My question is: how can I control the verbosity of make in a more "dynamic way", in order to be able to:

1. Normal behaviour: only a customized message is printed for every makefile rule executed.
2. Verbose behaviour: print the command actually executed by every makefile rule (as if the @ wasn't used at all).

Answer 1

Instead of using "@gcc" to compile, you can omit that "@" and pass the "-s" option to your make command instead. (Leave "@echo" as it is.) Then "make -s" would be your brief make command, and "make" would be verbose.

The ‘-s’ or ‘--silent’ flag to make prevents all echoing, as if all recipes started with ‘@’.

From the GNU Make manual pages

(The other answers better answer your question, but this approach deserves a mention.)

Answer 2

Another solution (one which I like because it's flexible)

ifeq ("$(BUILD_VERBOSE)","1")
Q :=
vecho = @echo
else
Q := @
vecho = @true
endif

%.o: %.c
    $(vecho) "-> Compiling $@"
    $(Q)$(CC) $(CFLAGS) -c $< -o $@

You can skip the vecho stuff, but it does come in handy at times.