ARM Banked register

Question

In ARM there is a concept of Banked Register. While reading many questions and their answer and various other resources about what is Banked mean here. Then I got this definition: Register banking refers to providing multiple copies of a register at the same address. Not all registers can be seen at once.

But my query here is that How multiple copies of registers are created. Because we have single register file in our core. And if there is another mode then it will get the new copy of the banked register that will not contain any data and not going to access the data of another mode register. Then how this copy of register is created?

Answer 1

Register banking refers to providing multiple copies of a register at the same address. Not all registers can be seen at once.

This is some what correct. However, the register does not have a 'traditional address'. The majority of the arm instructions or 'binary encodings' have register as source or destination arguments. There are sixteen base register so four bits are needed for each register in a binary instruction. A typical instruction takes 12 bits (out of 32bits) to describe the three registers (two source and one destination). These bits in the instruction are the 'address' in the definition above.

But my query here is that How multiple copies of registers are created. Because we have single register file in our core. And if there is another mode then it will get the new copy of the banked register that will not contain any data and not going to access the data of another mode register. Then how this copy of register is created?

They are not 'created' dynamically. The banked registers are part of the 'register file' of the core and always exist. The issue is that the typical instructions can not access some banked registers unless a 'mode switch' occurs. This maybe from user to IRQ mode or from normal to secure world with trustzone.

So running the same code in different modes may end up accessing different (banked) registers. In this way, user code never affects the IRQ stack and vice-versa. Perhaps more importantly, the IRQ code could corrupt non-banked user registers if careful context saving is not performed at the start and end of an IRQ.

See: Accessing banked registers on ARM for information on how you might access these different registers.

The newer ARMv7 instruction mrs r2,sp_svc breaks this banked register rule and allows access to the banked registers directly without switching a mode. the intent is to allow context switching code to easily access the banked registers for saving and restoring without a mode switch.

The traditional instruction ldm rN, {sp,lr}^ allows saving of user stack pointer and link register without switching modes. Again, this has a special encoding (or addressing as per your definition).

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Banking is also done with CP15 system registers in trustzone. TrustZone monitor mode and banked IFSR... maybe interesting for anyone looking at that ARM 'banking' which is conceptually the same as the register banking.

Answer 2

I count 31 registers needed to support the traditional arm. Several r13s and r14s a bunch for FIQ mode. First and foremost you are confusing tasks and modes. At the application level the tasks will all share the same set of registers, there is no banking there, when you switch tasks you have to save registers, the operating system allocates memory for this and for each task switch saves the old tasks registers and restores the next tasks registers.

As far as register banking there are multiple r13s for example. For each access to the register there is more than a simple offset into the register file it also has other inputs, for example

unsigned int get_r13 ( unsigned int mode )
{
switch(mode)
{
case SYS: return r13_sys;
case SVC: return r13_svc;
case ABT: return r13_abt;
case UND: return r13_und;
case IRQ: return r13_irq;
case FIQ: return r13_fiq;
}
}

but in logic although the logic could very well look about the same, that or they take the mode bits and logically convert them into some of the address bits into the register file or a combination thereof.

A single register file does not mean there are only 16 registers (r0-r15, not counting cpsr, etc) in the register file, there are 31 or more depending on whether or not it contains *PSR registers.