ARM AArch64 Assembly: immediate out of range

Question

I have a problem with using immediate values in AArch64 assembly instructions. I've googled it but couldn't find any solution. I want to simply AND a w register with an immediate value as follow:

"and w9, w8, #0x5fffffff \n\t"

This gives me immediate out of range at operand 3 error. Same situation happens when I want to xor an immediate value with x registers:

"eor x0, x0, #ffffffffffffffff"

Does anyone know why?

Answer 1

The A64 instruction set has very weird limitations on the kinds of immediates that can be use in instructions. The basic limitation is relatively straight forward, all instructions are 32 bits long and instructions can only use a small subset of those 32 bits for immediate values. The weird part is which immediate values are legal for which instruction. According to the ARM Compiler armasm Reference Guide, the AND and EOR instructions limit the immediate value to:

Such an immediate is a 32-bit or 64-bit pattern viewed as a vector of identical elements of size e = 2, 4, 8, 16, 32, or 64 bits. Each element contains the same sub-pattern: a single run of 1 to e-1 non-zero bits, rotated by 0 to e-1 bits. This mechanism can generate 5,334 unique 64-bit patterns (as 2,667 pairs of pattern and their bitwise inverse). Because the all-zeros and all-ones values cannot be described in this way, the assembler generates an error message.

For the first instruction you'll need to load the immediate value into another register first. Something like:

ldr w10, =0x5fffffff
and w9, w8, w10

For the second instruction you can replace it with the MVN (bitwise NOT) instruction:

mvn x0, x0

Note that the last instruction is actually an alias for the ORN (bitwise OR NOT) instruction:

orn x0, xzr, x0