Are C++ int operations atomic on the mips architecture

Question

I wonder if I could read or write shared int value without locking on mips cpu (especially Amazon or Danube). What I mean is if such a read or write are atomic (other thread can't interrupt them). To be clear - I don't want to prevent the race between threads, but I care if int value itself is not corrupted.

Assuming that the compiler aligns all ints at the boundaries of cpu word, it should be possible. I use gcc (g++). Tests also shows that it seems work correctly. But maybe someone knows it for sure?

Answer 1

Use gcc's builtin atomic operations and you'll get warnings if they're not supported: http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html

It looks like combinations of addition/subtraction and testing (at least) are possible on the hardware: http://rswiki.csie.org/lxr/http/source/include/asm-mips/atomic.h

Answer 2

Which operations? It's plausible that int a; a=42; is atomic. There's no guarantee that a= a+42; is atomic, or in any variants like with ++. Also, you have to be concerned about what the optimizer might do, say by holding an intermediate value in a register when convenient.