Will Peterson's solution work correctly on modern CPU architectures? [closed]

Question

I am studying operating systems from Operating System Concepts by Silberschatz, Galvin, and Gagne.

On page 229, the book states this about Petersons Solution :

Because of the way modern computer architectures perform basic machine language instructions, such as load and store, there are no guarantees that Peterson's solution will work correctly on such architectures.

I looked this up on Wikipedia and found this which appears to be the closest to an explanation :

Most modern CPUs reorder memory accesses to improve execution efficiency. Such processors invariably give some way to force ordering in a stream of memory accesses, typically through a memory barrier instruction. Implementation of Peterson's and related algorithms on processors which reorder memory accesses generally requires use of such operations to work correctly to keep sequential operations from happening in an incorrect order. Note that reordering of memory accesses can happen even on processors that don't reorder instructions

I am having trouble understanding what this means or if this is even the answer.

So, why is Peterson's solution not guaranteed to work on modern architectures ?

Answer 1

On a system with one CPU, Peterson's algorithm is guaranteed to work, because program's own behavior is observed in program order.

On systems with multiple CPUs the algorithm may fail to work because the program order of events occurring on one CPU may be perceived differently on another.

That may cause early entering into the critical section (while it's still in use by another thread) and early exiting from the critical section (when the work with the shared resource hasn't been finished yet).

For this reason one needs to ensure that the order of events occurring inside the CPU is seen the same outside. Memory barriers can ensure this serialization.