Menu
I am curious about why there are some ARM instuctions (like MUL and QADD) does not use barrel shifter. I would like to know the rational behind the limit. Thanks!
954
There are data processing instructions that do not use the barrel shift, for example, the MUL (multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add) instructions.
A barrel shifter is a digital circuit that can shift a data word by a specified number of bits without the use of any sequential logic, only pure combinational logic, i.e. it inherently provides a binary operation.
It is used in conjunction with a processor's arithmetic logic unit (ALU) or otherwise embedded in the ALU itself. A barrel shifter is able to shift the bits of binary data by moving it from one multiplexer to the next, with the supported number of bits dictated by how many multiplexers are used.
The Barrel Shifter is similar to the Shift Register (Multi-bit), except that bits shifted of the register are shifted back into the opposite end of the register. For example, in right shift operations, the LSBs shifted out of the register are shifted into the MSBs.
It's not that the barrel shifter isn't used; it's that you aren't able to specify how it's used in all but very specific instructions (data processing and load/store). If you look at the instruction encoding you'll see that there is just no room to specify it.
In the case of instructions like MUL or SWP, they were not in the first version of the architecture. They were squeezed into the instruction set by making use of otherwise invalid combinations of values for the specification of the barrel shifter. Since the barrel shifter specification bits had to be repurposed for storing things like what instruction to execute and what register to use as the multiplier, there was simply no way to specify how much to shift/rotate the operand.
143
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With
