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Naively, conditionally executed instructions seem like a great idea to me.
As I read more about ARM (and ARM-like) instruction sets (Thumb2, Unicore, AArch64) I find that they all lack the bits for conditional execution.
Why is conditional execution missing from each of these?
Was conditional execution a mistake at the time, or have subsequent changes made it an expensive waste of instruction bits?
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ARM PROCESSOR FUNDAMENTALS Conditional execution controls whether or not the core will execute an instruction. Most instructions have a condition attribute that determines if the core will execute it based on the setting of the condition flags.
You can use conditional execution of ARM instructions to reduce the number of branch instructions in your code. This improves code density. The IT instruction in Thumb achieves a similar improvement. Branch instructions are also expensive in processor cycles.
You can either add a condition code suffix to the instruction or you can conditionally skip over the instruction using a conditional branch instruction. Using conditional branch instructions to control the flow of execution can be more efficient when a series of instructions depend on the same condition.
Condition codes In ARM state, you can use a condition code to control the execution of VFP instructions. The instruction is executed conditionally, according to the status flags in the APSR, in exactly the same way as almost all other ARM instructions.
General claim is modern systems have better branch predictors and compilers are much more advanced so their cost on instruction encoding space is not justified.
This is from ARMv8 Instruction Set Overview
The A64 instruction set does not include the concept of predicated or conditional execution. Benchmarking shows that modern branch predictors work well enough that predicated execution of instructions does not offer sufficient benefit to justify its significant use of opcode space, and its implementation cost in advanced implementations.
And it continues
A very small set of “conditional data processing” instructions are provided. These instructions are unconditionally executed but use the condition flags as an extra input to the instruction. This set has been shown to be beneficial in situations where conditional branches predict poorly, or are otherwise inefficient.
Another paper titled Trading Conditional Execution for More Registers on ARM Processors claims:
... conditional execution takes up precious instruction space as conditions are encoded into a 4-bit condition code selector on every 32-bit ARM instruction. Besides, only small percentages of instructions are actually conditionalized in modern embedded applications, and conditional execution might not even lead to performance improvement on modern embedded processors.
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