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I understand the meaning of
obj-$(CONFIG_USB) += usb.o if CONFIG_USB is y then usb.o will be compiled. So now how to understand this
obj-y += something/ 
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1. From the Linux kernel documentation for obj-m: "$(obj-m) specifies object files that are built as kernel modules.". There isn't an obj-m+ . The + is part of the += operator to append to a variable. It can also be used to append subdirectories which will be entered recursively.
The top Makefile is responsible for building two major products: vmlinux (the resident kernel image) and modules (any module files). It builds these goals by recursively descending into the subdirectories of the kernel source tree. The list of subdirectories which are visited depends upon the kernel configuration.
"kbuild" is the build system used by the Linux kernel. Modules must use kbuild to stay compatible with changes in the build infrastructure and to pick up the right flags to "gcc." Functionality for building modules both in-tree and out-of-tree is provided.
uname provides the kernel version, the code goes on to use the unix sed (stream editor; man sed for more) to extract each of the major, minor and rev numbers from the results and assign them to discrete variable-like macros.
Kernel Makefiles are part of the kbuild system, documented in various places on the web, for example http://lwn.net/Articles/21835/. The relevant excerpt is here:
--- 3.1 Goal definitionsGoal definitions are the main part (heart) of the kbuild Makefile. These lines define the files to be built, any special compilation options, and any subdirectories to be entered recursively.
The most simple kbuild makefile contains one line:
Example: obj-y += foo.o
This tell kbuild that there is one object in that directory named foo.o. foo.o will be build from foo.c or foo.S.
If foo.o shall be built as a module, the variable obj-m is used. Therefore the following pattern is often used:
Example: obj-$(CONFIG_FOO) += foo.o
$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module). If CONFIG_FOO is neither y nor m, then the file will not be compiled nor linked.
So m means module, y means built-in (stands for yes in the kernel config process), and $(CONFIG_FOO) pulls the right answer from the normal config process.
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obj-y += something/
This means that kbuild should go into the directory "something". Once it moves to this directory, it looks at the Makefile in "something" to decide what objects should be built.
It is analogous to saying- go to the directory "something" and execute "make"
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