Whats meaning of obj-y += something/ in linux kernel Makefile?

Question

I understand the meaning of

obj-$(CONFIG_USB)       += usb.o 

if CONFIG_USB is y then usb.o will be compiled. So now how to understand this

obj-y               += something/ 

Answer 1

Kernel Makefiles are part of the kbuild system, documented in various places on the web, for example http://lwn.net/Articles/21835/. The relevant excerpt is here:

--- 3.1 Goal definitions 

Goal definitions are the main part (heart) of the kbuild Makefile. These lines define the files to be built, any special compilation options, and any subdirectories to be entered recursively.

The most simple kbuild makefile contains one line:

Example: obj-y += foo.o

This tell kbuild that there is one object in that directory named foo.o. foo.o will be build from foo.c or foo.S.

If foo.o shall be built as a module, the variable obj-m is used. Therefore the following pattern is often used:

Example: obj-$(CONFIG_FOO) += foo.o

$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module). If CONFIG_FOO is neither y nor m, then the file will not be compiled nor linked.

So m means module, y means built-in (stands for yes in the kernel config process), and $(CONFIG_FOO) pulls the right answer from the normal config process.

Answer 2

obj-y += something/

This means that kbuild should go into the directory "something". Once it moves to this directory, it looks at the Makefile in "something" to decide what objects should be built.

It is analogous to saying- go to the directory "something" and execute "make"