what is difference between Superscaling and pipelining?

Question

Well looks too simple a question to be asked but i asked after going through few ppts on both.

Both methods increase instruction throughput. And Superscaling almost always makes use of pipelining as well. Superscaling has more than one execution unit and so does pipelining or am I wrong here?

Answer 1

Superscalar design involves the processor being able to issue multiple instructions in a single clock, with redundant facilities to execute an instruction. We're talking about within a single core, mind you -- multicore processing is different.

Pipelining divides an instruction into steps, and since each step is executed in a different part of the processor, multiple instructions can be in different "phases" each clock.

They're almost always used together. This image from Wikipedia shows both concepts in use, as these concepts are best explained graphically:

Here, two instructions are being executed at a time in a five-stage pipeline.

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To break it down further, given your recent edit:

In the example above, an instruction goes through 5 stages to be "performed". These are IF (instruction fetch), ID (instruction decode), EX (execute), MEM (update memory), WB (writeback to cache).

In a very simple processor design, every clock a different stage would be completed so we'd have:

1. IF
2. ID
3. EX
4. MEM
5. WB

Which would do one instruction in five clocks. If we then add a redundant execution unit and introduce superscalar design, we'd have this, for two instructions A and B:

1. IF(A) IF(B)
2. ID(A) ID(B)
3. EX(A) EX(B)
4. MEM(A) MEM(B)
5. WB(A) WB(B)

Two instructions in five clocks -- a theoretical maximum gain of 100%.

Pipelining allows the parts to be executed simultaneously, so we would end up with something like (for ten instructions A through J):

1. IF(A) IF(B)
2. ID(A) ID(B) IF(C) IF(D)
3. EX(A) EX(B) ID(C) ID(D) IF(E) IF(F)
4. MEM(A) MEM(B) EX(C) EX(D) ID(E) ID(F) IF(G) IF(H)
5. WB(A) WB(B) MEM(C) MEM(D) EX(E) EX(F) ID(G) ID(H) IF(I) IF(J)
6. WB(C) WB(D) MEM(E) MEM(F) EX(G) EX(H) ID(I) ID(J)
7. WB(E) WB(F) MEM(G) MEM(H) EX(I) EX(J)
8. WB(G) WB(H) MEM(I) MEM(J)
9. WB(I) WB(J)

In nine clocks, we've executed ten instructions -- you can see where pipelining really moves things along. And that is an explanation of the example graphic, not how it's actually implemented in the field (that's black magic).

The Wikipedia articles for Superscalar and Instruction pipeline are pretty good.

Answer 2

A long time ago, CPUs executed only one machine instruction at a time. Only when it was completely finished did the CPU fetch the next instruction from memory (or, later, the instruction cache).

Eventually, someone noticed that this meant that most of a CPU did nothing most of the time, since there were several execution subunits (such as the instruction decoder, the integer arithmetic unit, and FP arithmetic unit, etc.) and executing an instruction kept only one of them busy at a time.

Thus, "simple" pipelining was born: once one instruction was done decoding and went on towards the next execution subunit, why not already fetch and decode the next instruction? If you had 10 such "stages", then by having each stage process a different instruction you could theoretically increase the instruction throughput tenfold without increasing the CPU clock at all! Of course, this only works flawlessly when there are no conditional jumps in the code (this led to a lot of extra effort to handle conditional jumps specially).

Later, with Moore's law continuing to be correct for longer than expected, CPU makers found themselves with ever more transistors to make use of and thought "why have only one of each execution subunit?". Thus, superscalar CPUs with multiple execution subunits able to do the same thing in parallel were born, and CPU designs became much, much more complex to distribute instructions across these fully parallel units while ensuring the results were the same as if the instructions had been executed sequentially.