Why do I need to make a make target
before being able to build my source code?
More specifically, what is make target exactly?
A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target.
Makefile sets a set of rules to determine which parts of a program need to be recompile, and issues command to recompile them. Makefile is a way of automating software building procedure and other complex tasks with dependencies. Makefile contains: dependency rules, macros and suffix(or implicit) rules.
By default, the goal is the first target in the makefile (not counting targets that start with a period). Therefore, makefiles are usually written so that the first target is for compiling the entire program or programs they describe.
Makefiles look like this:
all: mybinary mybinary: files.o it.o depends.o on.o [tab]$(CC) $(CFLAGS) files.o it.o depends.o on.o -o mybinary files.o: files.c files.h [tab]$(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@ ...
This means, when you type make all
(the shorthand is just to type make
), it will make sure that the mybinary target or file is up to date. To do that, it needs to make sure that mybinary is newer than all of files.o it.o depends.o and on.o. If not, then it uses the shell commands specified on the next line to build mybinary. But before doing that, it first makes sure that files.o and so on are up to date. This means they have to be newer than files.c and files.h. If not, then it uses the shell commands specified on the next line to build files.o. Once all the *.o files are up to date, it can build mybinary. Once mybinary is built, the all target is satisfied.
Targets are usually just files. The format of a block is:
target: list of dependency files [tab]shell commands to build target if it's older than any of its dependencies [tab]more shell commands [tab]still more
Targets can also be specified using wildcards, for instance %.c
means what in the shell you'd call *.c
.
Some targets are "phony" targets meaning they don't correspond to any real file. The "all" target is of this sort. So too is the "clean" target (make clean
). And so on. You don't really need or want to build a file called "all" or "clean". There are various ways to specify that a target is phony.
The first target to appear in the Makefile is the one that will be invoked if you simply type make
. One convention is to name this target "all". So then make
will be the same as make all
.
A 'make target' is basically a file that you want rebuilt.
Make can't divine what you want built, so you have to tell it, implicitly or explicitly, what it should build. Often, the first target in the file is a name such as 'all' and if you run 'make' without any explicit target, it will build the first target listed in the makefile. However, some makefiles do not specify any target; then you must specify one on the command line. Or, if you don't want the default target built, then you must specify the target that you do want built.
A target can also be 'phony', in the terms of GNU make. That is, it is a name that does not exist, and the rules do not create it, but it (the phony target) depends on a number of other files that do have rules associated with them. Indeed, the 'all' target is usually a phony target - there isn't a file called 'all' in most directories.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With