What does *.o/.suffixes in makefile mean?

Question

I have seen commands like this all over Makefiles, which I don't quite understand:

vpath.o: make.h config.h getopt.h gettext.h dep.h 

and

.SUFFIXES: .SUFFIXES:  .f  .o # # %------------------% # | Default command. | # %------------------% # .DEFAULT:     @$(ECHO) "Unknown target $@, try:  make help" # # %-------------------------------------------% # |  Command to build .o files from .f files. | # %-------------------------------------------% # .f.o:     @$(ECHO) Making $@ from $<     @$(FC) -c $(FFLAGS) $< 

What does the *.o and *.suffixes mean?

Note: The two commands are from different parts of the script.

Answer 1

The first line in your question is just a standard Makefile rule.

vpath.o: make.h config.h getopt.h gettext.h dep.h 

A .o file is an object file; it's an intermediate product in between your source files and the final compiled binary. It contains compiled code, but it hasn't been linked together into a complete library or binary yet. This rule just says that vpath.o depends on make.h, config.h, etc., and each time those are changed, it should be re-compiled. The commands necessary to build vpath.o should follow on subsequent lines, indented with a tab character. (Apologies if I'm repeating stuff you already know; I wasn't sure what part of that first line you were confused about).

The .SUFFIXES doesn't refer to an actual file suffix; it's just a special kind of rule in a makefile which is used for configure "suffix rules".

Suffix rules are rules of the form .a.b, such as you see with your .f.o rule. They are a way of telling make that any time you see, say, a .f file (the source file), you can make a .o file (the target file) from it by following that rule, where $< indicates the source file and $@ represents the target file.

the .SUFFIXES "target" is a way to define which suffixes you can use in your suffix rules. When used with no prerequisites, it clears the built in list of suffixes; when used with prerequisites, it adds those to its list of known suffixes that may be used in suffix rules.

In GNU make, you can use the more powerful and more clear % to form pattern rules, like:

%.o: %.c     gcc -c -o $@ $< 

which is the equivalent of the suffix rule:

.c.o:     gcc -c -o $@ $< 

See the GNU Make documentation for more information (but which also mentions GNU extensions), or the Single Unix Specification/POSIX for the common, portable syntax.

Answer 2

As already mentioned the line
.SUFFIXES:
would delete all the known suffixes. This is done so that the:

• default suffixes wouldn't interfere with your special suffixes.
• Different make programs have incompatible suffix lists and implicit rules, and this sometimes creates confusion or misbehavior General Conventions for Makefiles

If you are using GNU make it is better to use pattern rules instead of suffix rules as they (suffix rules) exist for compatiblity reasons.Also suffix rules cannot have prerequisites of their own.

So you would rewrite the suffix rule of form:

.f.o:
...

as a pattern rule of the form:

%.o:%.f:
...

Note that in suffix rules prerequisite prefix comes first and the target suffix comes second, where as with pattern rules it is the other way round (and less confusing).

If you plan to work more with makefiles, also check the book Managing Projects with GNU Make which is available online.