What do these Makefile constructs mean?

Question

Can someone help me figure out the following make file?

BINS=file1 file2 file3

all: $(BINS)

clean: 
        rm -f $(BINS) *~ 

$*: [email protected]
        gcc -g -o $@ $?

Here are my questions:

1. What is the -g option of gcc?
2. What are $* and $@
3. How does it know to execute the last target?

Thanks!

Answer 1

From the gcc and make documentation:

1. "-g Produce debugging information in the operating system's native format".

2. a. "$* The stem with which an implicit rule matches (see How Patterns Match). If the target is dir/a.foo.b and the target pattern is a.%.b then the stem is dir/foo. The stem is useful for constructing names of related files. In a static pattern rule, the stem is part of the file name that matched the '%' in the target pattern."

   b. "$@ The file name of the target of the rule. If the target is an archive member, then '$@' is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), '$@' is the name of whichever target caused the rule's commands to be run."

   c. "$? The names of all the prerequisites that are newer than the target, with spaces between them." (Not asked, but worth adding.)

3. "'all' Compile the entire program. This should be the default target."

This example makefile is a bit limited, since it seems to only build C programs. The GNU make has several more extensive examples that are useful for learning how to write makefiles.