VHDL Signed Values

Question

I have just started VHDL module in university and my lecturer isn't good a explaining things. How to I use/declare signed values in VHDL?

This is the basic code format I have been taught and I'm currently programming a 2bit subtractor. The information in other websites are quite confusing.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity TwoBitSubtractor is port(
    x,y     :in integer range 0 to 3;
    result  :out integer range 0 to 3);
end TwoBitSubtractor;

architecture gates of TwoBitSubtractor is
begin
    result<= x - y;
end gates;

Answer 1

You should use signed type for specifying signed values. Integer can also be used to declare values in a more human readable manner, but with that you are out of bit-level definitions, which is not desired in VHDL in my opinion. For example, you are ignoring the the amount of bits used for any signal with integer, which can be good for a high level language, but not too useful for VHDL.

library ieee;
use ieee.numeric_std.all;

entity TwoBitSubtractor is port(
    x      : in signed(2 downto 0);
    y      : in signed(2 downto 0);
    result : out signed(2 downto 0));
end TwoBitSubtractor;

architecture gates of TwoBitSubtractor is
begin
    result <= x - y;
end gates;

See the way they are declared within the entity port. More details on signed/unsigned, please check here

Also a working online simulation of TwoBitSubtractor with testbench, check here