VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Question

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc "floor(logtwo($MAXVAL))+1"}).

I'm aware I could do:

SIGNAL myLogicVector : STD_LOGIC_VECTOR(2 downto 0) := 5; 

with which I'd explicitly specify an array of three std_logic 'bits', and set initial value; then I could use REPORT to print out the length (in this case, 3):

report("Bit width of myLogicVector is "& integer'image(myLogicVector'length));

So far, so good. But, let's say I use an integer (number) type instead:

SIGNAL myInteger : NATURAL range 0 to 5 := 5;

I'm guessing that here the 'compiler' ('synthesizer') would automatically infer that it needs 3 bits of storage length, as this integer is ranged with values between 0 and 5. If that is the case, my question is: is it possible to somehow print out this bit width/length/size in a REPORT?

The trick is, of course, that something like this:

report("Bit width of myInteger is "& integer'image(myInteger'length));

... will fail (say, with "HDLParsers:3389 - Prefix of attribute 'length must be an array object"), since as far as I gather, all these attributes like 'length and 'range are applicable only to arrays (Understanding VHDL Attributes), whereas an integer (natural) is not an array - it is a number :) (VHDL vector integer conversion question)

Again, I'm aware I could possibly utilize a log2 (Computing the width of an unsigned variable from maximum value?) - but what I'd like is just to see quickly (during synthesis) how many 'bits' the 'synthesizer' allocated for an eventual synthesized design, and thus approx how much would be used in terms of final FPGA resources (especially if I'd use 'generics' to somehow calculate a particular max value for an integer).

Well, thanks in advance for any responses, Cheers!

EDIT: a bit of context: I'm using ISE Webpack 9.2; I'm trying to use 'generic' variables/constants as parameters, and then use equations to calculate max values for counters. This calculation, I guess occurs at 'compile' time (which would be 'Synthesize' in ISE - not 'Implement Design'), and so it is here where I want the report messages to occur (and I in fact got them so, for std_logic_vector proper, in the synthesis log - however, the same report messages for me occur at start of behavioral simulation too, which is fine).

And the goal of these report messages is to make sure both that my equations are OK, and that the synthesizer will not try to infer a 32-bit counter - even if I want to count just from 0 to 5 :)

Answer 1

In principle, the representation of a VHDL integer is undefined.

In practice, you can normally assume that a synthesis tool will use a 2's complement representation, taking into account the range constraint. Therefore, the relation between the range constraint and the implemented bit width is straightforward, even though reporting the bit width from within VHDL is not.