Variable substitution in Makefile target dependency

Question

I have a Makefile with targets that have associated dependencies. So I use lookup table like:

APPS = a b c

dependency.lookup.a := x
dependency.lookup.b := y
dependency.lookup.c := z

$(APPS): %: path/$(dependency.lookup.%).datafile
    do something with $(dependency.lookup.$@)

This makefile gives me error. *** No rule to make target 'path/.datafile'

Constraints: Only MinGW. can't use shell/MSYS. Also support FreeBSD.

Answer 1

This requires using Secondary Expansion feature:

.SECONDEXPANSION:
$(APPS): %: path/$$(dependency.loopup.$$*).datafile
    @echo "$@ depends on $^"

%.datafile : # Create one on demand for testing.
    mkdir -p ${@D}
    touch $@

Outputs:

mkdir -p path/
touch path/x.datafile
a depends on path/x.datafile

---

Alternatively, use regular dependencies:

a : path/x.datafile
b : path/y.datafile
c : path/z.datafile

$(APPS): % :
    @echo "$@ depends on $^"

The top 3 lines only add dependencies, the rule is specified separately. The output is the same.