Using the make command without makefiles?

Question

I was compiling some C code for an assignment and I ran "make codeFile", where "codeFile" was the name of my C program, and even though I didn't have a makefile, an executable was created, and it ran and worked correctly.

Does anyone know why this worked? Why does make compile something even if I don't have a makefile? The only reference I could find was this: http://daly.axiom-developer.org/TimothyDaly_files/class5/node5.html

Answer 1

Make has several pre-defined implicit rules. In particular, in your case, it uses two such rules when trying to determine what to do for the target codeFile:

%: %.o    # Link object file
    $(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)

%.o: %.c  # Compile C source code
    $(CC) $(CPPFLAGS) $(CFLAGS) -c