Me

By day I am a student trying my best to absorb what is around me.

By night I am a Rust, C, MMIX and Verilog programmer with a passion for understanding and implementing the low-level details behind the abstractions of modern computing.

Current Projects

• Implementing an MMIX architecture processor on an FPGA
  • Altera Cyclone V SX SoC
• Pure Rust termbox implementation: rustty