Typical L1 and L2 access latency for SoCs made of ARM Cortex-A9

Question

I am looking for L1 access latency and L2 access latency for SoCs made from ARM Cortex-A9 processors such as Nvidia Tegra 2 and Tegra 3 which have multiple ARM A9 processors.

I could find some information about the L1 and L2 size of those architectures, but I could not much information about the L1 and L2 access latency. The only reliable information I found is that "L2 cache latency is 2 cycles faster on Tegra 3 than 2, while L1 cache latencies haven't changed."

Here is mentioned that L2 on Tegra 2 has a latency of 25 cycles and here is mentioned that L1 has a latency of 4 cycles and L2 has a latency of 31 to 55 cycles. None of these references are fully reliable. I was hoping to find more info on Nvidia, TI, and Qualcomm websites and technical documents, but no success.

EDIT: information on similar SoCs like OMAP4460 and OMAP4470 would be great too.

Answer 1

For an authoritative answer, you can try running lmbench (HowTo?) on the target of your choice.

A set of results for AM37x (variant of TI OMAP3 family) is available here for reference.

Also checkout this presentation that describes the latency and bandwidth of various caches configurations on an ARM Cortex A9 MP system.