I have more or less theoretical question regarding Cortex-M exceptions (IRQ interrupts). Assume we have two external interrupts PINT0 and PINT1 triggered by the same external signal. Both interrupts have (in NVIC register IPR0) set the same priority, let's say 0 (default). How NVIC handles this situation? Does the NVIC vector number of these two interrupts have any influence?
Thanks!
Depending on which version of the NVIC you have (i.e. Cortex M3 vs Cortex M0), there is the interrupt priority, there may be a subpriority, and lastly there would be a hardware priority.
Interrupt Priority
The priority you're referring to is the interrupt priority. An interrupt request of a higher priority than the current context (whether a non-interrupt, or an interrupt) will interrupt that context. Interrupt requests with the same priority as the current context will not interrupt. In the case you describe, one interrupt would always be serviced first, then the other. Which one is serviced first depends on some other factors...
Subpriority
Some variants of the NVIC have subpriorities. The subpriorities exist for just this sort of situation. You have two interrupts, you don't want one to interrupt the other, but you want to ensure that one will be serviced before the other if both are pending. The subpriority allows you to specify just this. In your example, if they have different subpriorities, the one with the higher subpriority (lower number) would be serviced first. If they're the same, then there's one last factor...
Hardware Priority
You hit the nail on the head in your post. If subpriority is not a factor, or the subpriority is also equal, then the request number in the NVIC is the last factor, where lower request numbers have a higher hardware priority.
In the specific situation you describe, where both have IPR set to zero, that means both the priority and any subpriority for both will be zero, and so the hardware priority would break the "tie", and the lower request number would be serviced first.
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