I'm trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I'm trying to use target-specific variables to represent these variations. Some of these variable values refer to files I want to use as prerequisites. For example:
target_1:special_filename=target1_prereq
target_2:special_filename=target2_prereq
target_1 target_2: common_filename $(special_filename)
do_something common_filename --a-weird-option=$(special_filename)
When I call 'make target_1', I want it to make target1_prereq if it doesn't exist. At the moment, it doesn't seem to use target1_prereq as a prerequisite, even though the build command (do_something) is called with the right parameter.
I'm using GNU Make 3.80.
Edit: A few more complications from the real system. Some of the variables are themselves based on the values of other variables. Manually specifying the prerequisites wouldn't scale. A slightly more complicated example:
target_1:special_filename_base=target1_prereq
target_2:special_filename_base=target2_prereq
some_filename_a = $(special_filename_base).exta
some_filename_b = $(special_filename_base).extb
target_1 target_2: common_filename $(special_filename_b) $(special_filename_a)
do_something common_filename --a-weird-option=$(special_filename_a) --second=$(special_filename_b)
A simple makefile consists of “rules” with the following shape: target … : prerequisites … recipe … … A target is usually the name of a file that is generated by a program; examples of targets are executable or object files.
There is one way that the makefile can change a variable that you have overridden. This is to use the override directive, which is a line that looks like this: ' override variable = value ' (see The override Directive).
MAKECMDGOALS. The targets given to make on the command line. Setting this variable has no effect on the operation of make. See Arguments to Specify the Goals.
A target-specific variable is defined only in the target's commands (or in other target-specific assignments); it can't be used as one of the target's prereqs. I don't think there's a clean way to do what you want in Make, but there are several kludgey approaches, such as the following:
EXTENSIONS = .exta .extb target_1: $(addprefix target1_prereq,$(EXTENSIONS)) target_2: $(addprefix target2_prereq,$(EXTENSIONS)) target_1 target_2: common_filename do_something common_filename --a-weird-option=$(filter %.exta,$^) --second=$(filter %.extb,$^)
As a simple workaround:
target_1:special_filename=target1_prereq target_1:target1_prereq target_2:special_filename=target2_prereq target_2:target2_prereq target_1 target_2: common_filename $(special_filename) do_something common_filename --a-weird-option=$(special_filename)
There is some redundancy, but it is localized, so it's not too bad.
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